Improvements in Integrated Circuit Patterning

Pushing Multiple Patterning in Sub-10nm: Are We Ready? (Invited Paper)

Due to elongated delay of extreme ultraviolet lithography (EUVL), the semiconductor industry has been pushing the 193nm immersion lithopgrahy using multiple patterning to print critical features in 22nm/14nm technology nodes and beyond. Multiple patterning lithography (MPL) poses many new challenges to both mask design and IC physical design. The mask layout decomposition problem has been exten...

Sub-10 nm colloidal lithography for circuit-integrated spin-photo-electronic devices

Patterning of materials at sub-10 nm dimensions is at the forefront of nanotechnology and employs techniques of various complexity, efficiency, areal scale, and cost. Colloid-based patterning is known to be capable of producing individual sub-10 nm objects. However, ordered, large-area nano-arrays, fully integrated into photonic or electronic devices have remained a challenging task. In this wo...

Nanolithography and nanopatterning The capability to modify the surface of a material by patterning the surface has a paramount importance in many fields of science and technology. This technique is applied in the fabrication of integrated circuits

A Compact Wide Bandpass Filter based on Substrate Integrated Waveguide (SIW) Structure

In this pare, a wideband three-order bandpass filter (BPF) is proposed. The proposed wideband filter is designed using the substrate integrated waveguide (SIW) structure by loading T-shape slots. A BPF with two resonators is formed by etching T-shape slots with different size on the top metal plane of the SIW structure. The filter is investigated with the theory of coupled resonator circuits. T...

Design Investigation of Microstrip Patch and Half-Mode Substrate Integrated Waveguide Cavity Hybrid Antenna Arrays

In this paper two linear arrays including a linear 1×4 and a planar 2×2 of microstrip patch and half-mode substrate integrated waveguide (SIW) cavity hybrid antenna are introduced and investigated. These are simply implemented using low cost single layer printed circuit board (PCB) process. The array element consists of a rectangular microstrip patch with appropriate dimensions in the vicinity ...